diff --git a/vlib/v/gen/native/amd64.v b/vlib/v/gen/native/amd64.v
index cb3896e6cb..423f089bc3 100644
--- a/vlib/v/gen/native/amd64.v
+++ b/vlib/v/gen/native/amd64.v
@@ -234,7 +234,7 @@ fn (mut g Gen) mov64(reg Register, val i64) {
 fn (mut g Gen) mov_reg_to_var(var_offset int, reg Register) {
 	// 89 7d fc     mov DWORD PTR [rbp-0x4],edi
 	match reg {
-		.rax, .rsi {
+		.rax {
 			g.write8(0x48)
 		}
 		else {}
@@ -642,7 +642,7 @@ fn (mut g Gen) mov(reg Register, val int) {
 				g.write8(0xba)
 			}
 			.rsi {
-				g.write8(0x48)
+				//	g.write8(0x48) // its 32bit!
 				g.write8(0xbe)
 			}
 			.r12 {
diff --git a/vlib/v/gen/native/tests/sumcall.vv b/vlib/v/gen/native/tests/sumcall.vv
new file mode 100644
index 0000000000..b91f941c67
--- /dev/null
+++ b/vlib/v/gen/native/tests/sumcall.vv
@@ -0,0 +1,19 @@
+fn sumcall(a int, b int) int {
+	r := a + b
+	return r
+}
+
+fn sumcall2(a int, b int) int {
+	return a + b
+}
+
+fn main() {
+	r := sumcall (1,2)
+	assert r == 3
+/*
+	// XXX not yet working
+	s := sumcall2 (1,2)
+	assert r == 3
+*/
+	exit(0)
+}
diff --git a/vlib/v/gen/native/tests/sumcall.vv.out b/vlib/v/gen/native/tests/sumcall.vv.out
new file mode 100644
index 0000000000..e69de29bb2