cgen: fix match sumtype var aggregate str_intp error (#12732)

vlib/v/gen/c/str_intp.v

@@ -151,9 +151,16 @@ fn (mut g Gen) str_val(node ast.StringInterLiteral, i int) {
 		g.write(')')
 	} else if node.fmts[i] == `s` || typ.has_flag(.variadic) {
 		mut exp_typ := typ
-		if expr is ast.Ident && g.comptime_var_type_map.len > 0 {
+		if expr is ast.Ident {
 			if expr.obj is ast.Var {
-				exp_typ = expr.obj.typ
+				if g.comptime_var_type_map.len > 0 {
+					exp_typ = expr.obj.typ
+				} else if expr.obj.smartcasts.len > 0 {
+					cast_sym := g.table.get_type_symbol(expr.obj.smartcasts.last())
+					if cast_sym.info is ast.Aggregate {
+						exp_typ = cast_sym.info.types[g.aggregate_type_idx]
+					}
+				}
 			}
 		}
 		g.gen_expr_to_string(expr, exp_typ)

vlib/v/tests/match_sumtype_var_aggregate_print_var_test.v

@@ -1,13 +0,0 @@
-type Bug = i64 | u64
-
-fn test_match_sumtype_var_aggregate_print_var() {
-	f := Bug(i64(-17))
-	ret := match f {
-		u64, i64 {
-			println(f)
-			println(f.str())
-			f.str()
-		}
-	}
-	assert ret == '-17'
-}

vlib/v/tests/match_sumtype_var_aggregate_var_str_test.v

@@ -0,0 +1,23 @@
+type Bug = i64 | u64
+
+fn test_match_sumtype_var_aggregate_print_var() {
+	f1 := Bug(i64(-17))
+	ret1 := match f1 {
+		u64, i64 {
+			println(f1)
+			println(f1.str())
+			f1.str()
+		}
+	}
+	assert ret1 == '-17'
+
+	f2 := Bug(i64(-18))
+	ret2 := match f2 {
+		u64, i64 {
+			println(f2)
+			println('$f2')
+			'$f2'
+		}
+	}
+	assert ret2 == '-18'
+}